This relates to, and claims priority of, Korean Patent Application No. 2001-0056518, filed on Sep. 13, 2001, the disclosure of which is hereby incorporated by reference.
The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a polysilicon electrode.
Bipolar transistors having an emitter, a base and a collector formed in a semiconductor substrate may be generally classified into vertical and lateral types based on the moving direction of charge carriers from the emitter. The carriers of a vertical transistor generally flow in a direction perpendicular to a surface of a substrate having the transistor, while those of the lateral transistor flow parallel to the surface. When using a P-type substrate, an NPN transistor is typically a vertical type, while a PNP transistor is typically a lateral type.
N-type and P-type resistors, as well as PNP and NPN transistors, may be generally provided in a single substrate, and the manufacturing method thereof typically requires several photolithography steps. According to one conventional design, when a transistor having a polysilicon emitter electrode and a polysilicon resistor is formed in a single substrate, at least thirteen (13) lithography steps, including a step for forming metal electrodes, are needed.
In general, according to some embodiments, the present method provides for the manufacture of a semiconductor device with a reduced number of lithography steps and for self-alignment of intrinsic and extrinsic base regions of a vertical bipolar transistor.
According to one aspect, an emitter region and a base region of different conductivity types for a vertical bipolar transistor may be formed simultaneously by counter doping, i.e., implanting two different conductivity type impurities with different doses into a polysilicon layer and diffusing the impurities into a semiconductor body.
According to another aspect, an extrinsic base region may be formed by using a polysilicon emitter electrode or a photoresist pattern thereon as a mask. Specifically, a photoresist pattern is formed on a polysilicon layer over a semiconductor body. The polysilicon layer is then etched by using the photoresist pattern as an etch mask to form a polysilicon electrode, and impurity is implanted or diffused into the semiconductor body using the photoresist pattern as a mask.
According to yet another aspect, a polysilicon electrode and a polysilicon resistor are formed using a single lithography step. A first dose of an impurity of a first conductivity type is implanted or diffused into a polysilicon layer and a second dose of an impurity of a second conductivity type is implanted or diffused into a portion of the polysilicon layer. The polysilicon layer is then patterned to form the electrode and the resistor.
According to still another embodiment, a collector region of a first conductivity type is formed in a semiconductor body of the first conductivity type. After depositing a polysilicon layer on the semiconductor body, a first dose of a first impurity of a second conductivity type is introduced into the polysilicon layer. In addition, a second dose of the second impurity of the first conductivity type is introduced into the polysilicon layer with the second dose being greater than the first dose. By patterning the polysilicon layer, a collector poly and an emitter poly spaced apart from each other are formed. The semiconductor body is then subjected to heat treatment, which forms an emitter region of the first conductivity type under the emitter poly and a base region of the second conductivity type under the emitter region.
The impurity of the second conductivity type may be introduced into the semiconductor layer after forming the emitter poly and before the heat treatment, to form an extrinsic base region after the heat treatment.
The patterning the polysilicon layer may include forming a photoresist pattern on the polysilicon layer, etching the polysilicon layer, introducing the second-conductivity-type impurity into the semiconductor body using the photoresist pattern as a mask, and removing the photoresist pattern.
Pursuant to a particular embodiment, the diffusion rate of the first impurity may be larger than that of the second impurity.
According to yet another aspect, the semiconductor device may have a semiconductor substrate of the second conductivity type disposed under the semiconductor body where the semiconductor body comprises an epitaxial layer. In addition, a buried layer of the first conductivity type connected to the collector region may be provided in the substrate and the epitaxial layer.
The manufacturing method may also include implanting an impurity of the second conductivity type for the base region into the semiconductor body before depositing the polysilicon layer.
The method according to the present invention may also include forming a pad layer on the semiconductor body before forming the collector region. The pad layer may be removed before depositing the polysilicon layer. Alternatively, two contact holes may be formed in the pad layer, exposing portions of the collector region and another portion of the epitaxial layer. In the latter case, the polysilicon layer contacts the epitaxial layer through the contact holes.
In a specific example embodiment, the second dose is about 1.0-5.0xc3x971014 atoms/cm2 and the first dose is about 9.0xc3x971015-1.0xc3x971016 atoms/cm2.
The polysilicon layer may have a first portion which is not subjected to the introduction of the second impurity, and the first portion of the polysilicon layer may become a resistor of the second conductivity type, which is separated from the emitter and the collector poly after patterning the polysilicon layer.
According to another aspect, a method for manufacturing a semiconductor device includes forming a collector region of a first conductivity type in a semiconductor body of the first conductivity type. After depositing a polysilicon layer on the semiconductor body, a photoresist pattern is formed on the polysilicon layer. The polysilicon layer is then etched to form an emitter poly by using the photoresist pattern as an etch mask. A first impurity of a second conductivity type is introduced into the semiconductor body by using the photoresist pattern a mask for an extrinsic base region. After removing the photoresist pattern, an emitter region of the first conductivity type, an intrinsic base region of the second conductivity type, and the extrinsic base region connected to the intrinsic base region are formed.
A second impurity of the second conductivity type may be introduced into at least a first portion of the polysilicon layer before forming the photoresist pattern. Thereafter, a third impurity of the first conductivity type may be introduced into the polysilicon layer except for at least the first portion of the polysilicon layer before forming the photoresist pattern. Then, the etching forms a resistor of the first portion of the polysilicon layer separated from the emitter poly.
According to another aspect, a collector region of the first conductivity type is formed in a semiconductor body of the first conductivity type. Deposition of a polysilicon layer on the semiconductor body is followed by introduction of the second conductivity type impurity into the polysilicon layer without using photolithography. After forming a photoresist pattern covering at least one portion of the polysilicon layer, an impurity of the first conductivity type is introduced into the polysilicon layer using the photoresist pattern as a mask. The photoresist pattern is then removed, and the polysilicon layer is patterned to form a collector poly and an emitter poly of the first conductivity type and a resistor of the second conductivity type, which are spaced apart from one another.
Pursuant to another aspect, a semiconductor device may be manufactured by forming first and second sink regions in a semiconductor body having an insulating layer thereon. The semiconductor body may have vertical and lateral regions where the first and the second sink regions are formed, respectively. A first photoresist pattern may be formed on the insulating layer. The first photoresist pattern may have openings that expose at least a first portion of the insulating layer on a portion of the semiconductor body in the vertical region and second and third portions of the insulating layer on the first and the second sink regions.
The insulating layer is then etched using the first photoresist pattern. Then, after removing the first photoresist pattern, a polysilicon layer is deposited. A first dose of an impurity of second conductivity type is introduced into the polysilicon layer without any lithography mask. A second photoresist pattern is formed that covers at least a first portion of the polysilicon layer. A second dose of an impurity of the first conductivity type is introduced into the polysilicon layer by using the second photoresist pattern as a mask with the second dose being greater than the first dose.
A third photoresist pattern is then formed after removing the second photoresist pattern. The polysilicon layer is then etched using the third photoresist pattern as an etch mask to form first, second and emitter polys and a first resistor of the first conductivity type and a second resistor of the second conductivity type corresponding to the first portion of the polysilicon layer. The first, the second and the emitter polys and the first and the second resistors are spaced apart from one another, and the first and the second polys contacting the first and the second sink regions, respectively. An impurity of the second conductivity type is introduced into the semiconductor body using the third photoresist pattern a mask and then the third photoresist pattern is removed.
The semiconductor body is then heat treated to form an emitter region of the first conductivity type under the emitter poly, an intrinsic base region of the second conductivity type under the emitter region, and an extrinsic base region of the second conductivity type at a periphery of the intrinsic base region.
Details regarding the present apparatus and method may be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.